Modern digital circuits, whether implemented in integrated circuits (IC) or in discrete form, often utilize data latches. Two of the most common types of data latches in use today are the level-sensitive (LS) latch and the edge-triggered (ET) latch.
The logic output of an LS latch generally depends upon the activity of the clock signal that is present at its clock input pin. In particular, the output logic state of the LS latch reflects the logic state present at its input pin during a portion of the input clock cycle. In this phase of operation, the latch becomes transparent and passes logic values present at its input directly to its output. In a second phase of operation, the LS latch maintains its output at a fixed logic level during the remaining portion of the input clock cycle, regardless of the logic level present at its input.
One implementation of an ET latch includes a combination of two LS latches. The first LS latch, i.e., the master stage, is transparent during a first phase of the input clock, while the second LS latch, i.e., the slave stage, is transparent during a second phase of the input clock. The combined behavior is such that the input data is captured and passed to the output only when the clock signal exhibits a low-to-high logic transition. Conversely, the configuration of the two LS latches may be altered to capture input data during a high-to-low logic transition.
Often, the master-slave stages are used in parallel configuration to implement a double data rate (DDR) latch topology. In particular, a serial data stream may be broken out into two serial data streams, whereby a first DDR latch accepts, for example, the even bits of the serial data stream, while a second DDR latch accepts the odd bits of the serial data stream. After the two DDR latches have latched their respective data bits, the data bits may be retrieved from each latch and then re-combined into a single data stream through the use of, for example, a 2:1 multiplexer. Thus, in order to implement the DDR latch, a dual latch configuration is often used, which combines two master stages, two slaves stages, and a single 2:1 multiplexer.
In IC implementations, however, latches are often used in large numbers. Accordingly, a significant amount of semiconductor die area is required due to the redundancy of the design implementation. Similarly, the amount of power consumed by these implementations generally increases in linear proportion to the number of latches implemented.